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www.fairchildsemi.com
LMV321, LMV358, LMV324
General Purpose, Low Voltage, Rail-to-Rail Output Amplifiers
Features at +2.7V
* * * * * * * * * * 80A supply current per channel 1.2MHz gain bandwidth product Output voltage range: 0.01V to 2.69V Input voltage range: -0.25V to +1.5V 1.5V/s slew rate LMV321 directly replaces other industry standard LMV321 amplifiers; available in SC70-5 and SOT23-5 packages LMV358 directly replaces other industry standard LMV358 amplifiers; available in MSOP-8 and SOIC-8 packages LMV324 directly replaces other industry standard LMV324 amplifiers; available in TSSOP-14 and SOIC-14 packages Fully specified at +2.7V and +5V supplies Operating temperature range: -40C to +125C
Description
The LMV321 (single), LMV358 (dual), and LMV324 (quad) are a low cost, voltage feedback amplifiers that consume only 80A of supply current per amplifier. The LMV3XX family is designed to operate from 2.7V (1.35V) to 5.5V (2.75V) supplies. The common mode voltage range extends below the negative rail and the output provides rail-to-rail performance. The LMV3XX family is designed on a CMOS process and provides 1.2MHz of bandwidth and 1.5V/s of slew rate at a low supply voltage of 2.7V. The combination of low power, rail-to-rail performance, low voltage operation, and tiny package options make the LMV3XX family well suited for use in personal electronics equipment such as cellular handsets, pagers, PDAs, and other battery powered applications.
Frequency Response vs. CL
CL = 200pF Rs = 0 CL = 200pF Rs = 225 CL = 100pF Rs = 0 CL = 20pF Rs = 0 CL = 10pF Rs = 0 CL = 2pF Rs = 0
CL 2k
Applications
* * * * * * * * * * * * * * Low cost general purpose applications Cellular phones Personal data assistants A/D buffer DSP interface Smart card readers Portable test instruments Keyless entry Infrared receivers for remote controls Telephone systems Audio applications Digital still cameras Hard disk drives MP3 players
Magnitude (1dB/div)
CL = 50pF Rs = 0
+ 10k 10k
Rs
0.01
0.1
1
10
Frequency (MHz)
Typical Application
+Vs 6.8F
+
+In
+ Rg
0.01F Out Rf
LMV3XX
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DATA SHEET
LMV321/LMV358/LMV324
Pin Assignments
LMV321
SOT23-5 SC70-5
+In -Vs -In
1
+
5
+Vs
+In -Vs
1
+
5
+Vs
2 3
-
2 3
-
4
Out
-In
4
Out
LMV358
SOIC-8 MSOP-8
Out1 -In1 +In1 -Vs
1 2 3 4
+
8 7
+
+Vs Out2 -In2 +In2
Out1 -In1 +In1 -Vs
1 2 3 4
+
8 7
+
+Vs Out2 -In2 +In2
6 5
6 5
LMV324
TSSOP-14 SOIC-14
Out1 -In1 +In1 +Vs +In2 -In2 Out2
1 2 3 4
+ + + +
14 Out4 13 -In4 12 +In4 11 -Vs 10 +In3 9 8 -In3 Out3
Out1 -In1 +In1 +Vs +In2 -In2 Out2
1 2 3 4
+ + + +
14 Out4 13 -In4 12 +In4 11 -Vs 10 +In3 9 8 -In3 Out3
5 6 7
5 6 7
2
-
-
-
-
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LMV321/LMV358/LMV324
DATA SHEET
Absolute Maximum Ratings
Parameter Supply Voltages Maximum Junction Temperature Storage Temperature Range Lead Temperature, 10 seconds Input Voltage Range Min. 0 - -65 - -Vs -0.5 Max. +6 +175 +150 +260 +Vs +0.5 Unit V C C C V
Recommended Operating Conditions
Parameter Operating Temperature Range Power Supply Operating Range Min. -40 2.5 Max. +125 5.5 Unit C V
Electrical Specifications
(Tc = 25C, Vs = +2.7V, G = 2, RL = 10k to Vs/2, Rf = 10k, Vo (DC) = Vcc/2; unless otherwise noted) Parameter AC Performance Gain Bandwidth Product Phase Margin Gain Margin Slew Rate Input Voltage Noise Crosstalk: LMV358 LMV324 DC Performance Input Offset Voltage1 Average Drift Input Bias Current2 Input Offset Current2 Power Supply Rejection Ratio1 Supply Current (Per Channel)1 Input Characteristics Input Common Mode Voltage Range1 Common Mode Rejection Ratio1 Output Characteristics Output Voltage Swing Conditions CL = 50pF, RL = 2k to Vs/2 Min. Typ. 1.2 52 17 1.5 36 91 80 1.7 8 <1 <1 65 80 -0.25 1.5 70 0.01 2.69 7 Max. Unit MHz deg dB V/s nV/Hz dB dB mV V/C nA nA dB A V V dB V V
Vo = 1Vpp >50kHz 100kHz 100kHz
DC
50
120
LO HI
0 50
1.3
RL = 10k to Vs/2; LO1 RL = 10k to Vs/2; HI1
0.1
2.6
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Notes: 1. Guaranteed by testing or statistical analysis at +25C. 2. +IN and -IN are gates to CMOS transistors with typical input bias current of <1nA. CMOS leakage is too small to practically measure.
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3
DATA SHEET
LMV321/LMV358/LMV324
Electrical Specifications
(Tc = 25C, Vs = +5V, G = 2, RL = 10k to Vs/2, Rf = 10k, Vo (DC) = Vcc/2; unless otherwise noted) Parameter AC Performance Gain Bandwidth Product Phase Margin Gain Margin Slew Rate Input Voltage Noise Crosstalk: LMV358 LMV324 DC Performance Input Offset Voltage1 Average Drift Input Bias Current2 Input Offset Current2 Power Supply Rejection Ratio1 Open Loop Gain1 Supply Current (Per Channel)1 Input Characteristics Input Common Mode Voltage Range1 Common Mode Rejection Ratio1 Output Characteristics Output Voltage Swing Conditions CL = 50pF, RL = 2k to Vs/2 Min. Typ. 1.4 73 12 1.5 33 91 80 1 6 <1 <1 65 70 100 -0.4 3.8 75 0.036 to 4.95 0.013 4.98 +34 -23 7 Max. Unit MHz deg dB V/s nV/Hz dB dB mV V/C nA nA dB dB A V V dB V V V mA mA
>50kHz 100kHz 100kHz
DC
50 50
150
LO HI
0 50
3.6
Short Circuit Output Current1
RL = 2k to Vs/2; LO/HI RL = 10k to Vs/2; LO1 RL = 10k to Vs/2; HI1 sourcing; Vo = 0V sinking; Vo = 5V
0.1 5 10
4.9
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Notes: 1. Guaranteed by testing or statistical analysis at +25C. 2. +IN and -IN are gates to CMOS transistors with typical input bias current of <1nA. CMOS leakage is too small to practically measure.
Package Thermal Resistance
Package 5 lead SC70 5 lead SOT23 8 lead SOIC 8 lead MSOP 14 lead TSSOP 14 lead SOIC JA 331.4C/W 256C/W 152C/W 206C/W 100C/W 88C/W
4
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LMV321/LMV358/LMV324
DATA SHEET
Typical Operating Characteristics
(Tc = 25C, Vs = +5V, G = 2, RL = 10k to Vs/2, Rf = 10k, Vo (DC) = Vcc/2; unless otherwise noted)
Non-Inverting Freq. Response Vs = +5V
Normalized Magnitude (1dB/div)
G=2 G=1
Inverting Frequency Response Vs = +5V
Normalized Magnitude (1dB/div)
G = -2 G = -1
G = 10
G = -10 G = -5
G=5
0.01
0.1
1
10
0.01
0.1
1
10
Frequency (MHz) Non-Inverting Freq. Response Vs = +2.7V
Normalized Magnitude (1dB/div)
G=1 G=2
Frequency (MHz) Inverting Freq. Response Vs = +2.7V
Normalized Magnitude (1dB/div)
G = -1 G = -2 G = -10
G = 10
G=5
G = -5
0.01
0.1
1
10
0.01
0.1
1
10
Frequency (MHz) Frequency Response vs. CL
CL = 200pF Rs = 0 CL = 200pF Rs = 225 CL = 100pF Rs = 0 CL = 20pF Rs = 0 CL = 10pF Rs = 0 CL = 2pF Rs = 0
CL 2k
Frequency (MHz) Frequency Response vs. RL
Magnitude (1dB/div)
Magnitude (1dB/div)
CL = 50pF Rs = 0
RL = 1k
RL = 100k
RL = 10k
+ 10k 10k
Rs
RL = 2k
0.01
0.1
1
10
0.01
0.1
1
10
Frequency (MHz) Small Signal Pulse Response
0.25 0.2 2.5 2
Frequency (MHz) Large Signal Pulse Response
Output (V)
Output (V)
0.15 0.1 0.05 0
1.5 0.1 0.5 0 -0.5
-0.05 0 2 4 6 8 10 12 14 16 18 20
0
2
4
6
8
10
12
14
16
18
20
Time (s)
Time (s)
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DATA SHEET
LMV321/LMV358/LMV324
Typical Operating Characteristics
(Tc = 25C, Vs = +5V, G = 2, RL = 10k to Vs/2, Rf = 10k, Vo (DC) = Vcc/2; unless otherwise noted)
Input Voltage Noise
100 80 70 60 50 40 30 20 1 10 100 1000 0.6
Vo = 1Vpp
Total Harmonic Distortion
0.5 0.4
THD (%)
nV/Hz
0.3 0.2 0.1 0 0.1 1 10 100
Frequency (kHz) Open Loop Gain & Phase vs. Frequency
0
RL = 2k CL = 50pF
Frequency (kHz)
100 80
Open Loop Phase (deg)
-45 -90 -135 -180 -225 -270 10 100 1k 10k 100k 1M 10M
|Gain| Phase
Open Loop Gain (dB)
60 40 20 0 -20
Frequency (Hz)
6
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LMV321/LMV358/LMV324
DATA SHEET
Application Information
General Description
The LMV3XX family are single supply, general purpose, voltage-feedback amplifiers that are pin-for-pin compatible and drop in replacements with other industry standard LMV321, LMV358, and LMV324 amplifiers. The LMV3XX family is fabricated on a CMOS process, features a rail-to-rail output, and is unity gain stable. The typical non-inverting circuit schematic is shown in Figure
+
LMV3XX
Rs CL 2k
10k 10k
+Vs 6.8F
+
Figure 2: Typical Topology for driving a capacitive load
3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 0.01
Magnitude (dB)
+In
+ Rg
0.01F Out Rf
CL = 50pF Rs = 0 CL = 100pF Rs = 400 CL = 200pF Rs = 450
LMV3XX
0.1
1
10
Frequency (MHz )
1. Figure 1: Typical Non-inverting configuration
Figure 3: Frequency Response vs CL for unity gain configuration
Power Dissipation
The maximum internal power dissipation allowed is directly related to the maximum junction temperature. If the maximum junction temperature exceeds 150C, some performance degradation will occur. If the maximum junction temperature exceeds 175C for an extended time, device failure may occur.
Layout Considerations
General layout and supply bypassing play major roles in high frequency performance. Fairchild has evaluation boards to use as a guide for high frequency layout and as aid in device testing and characterization. Follow the steps below as a basis for high frequency layout: * Include 6.8F and 0.01F ceramic capacitors * Place the 6.8F capacitor within 0.75 inches of the power pin * Place the 0.01F capacitor within 0.1 inches of the power pin * Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance * Minimize all trace lengths to reduce series inductances Refer to the evaluation board layouts shown in Figure 5 on page 8 for more information.
Driving Capacitive Loads
The Frequency Response vs CL plot on page 4, illustrates the response of the LMV3XX family. A small series resistance (Rs) at the output of the amplifier, illustrated in Figure 2, will improve stability and settling performance. Rs values in the Frequency Response vs CL plot were chosen to achieve maximum bandwidth with less than 1dB of peaking. For maximum flatness, use a larger Rs. As the plot indicates, the LMV3XX family can easily drive a 200pF capacitive load without a series resistance. For comparison, the plot also shows the LMV321 driving a 200pF load with a 225 series resistance. Driving a capacitive load introduces phase-lag into the output signal, which reduces phase margin in the amplifier. The unity gain follower is the most sensitive configuration. In a unity gain follower configuration, the LMV3XX family requires a 450 series resistor to drive a 200pF load. The response is illustrated in Figure 3.
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7
DATA SHEET
LMV321/LMV358/LMV324
Evaluation Board Information
The following evaluation boards are available to aid in the testing and layout of this device:
Eval Bd KEB013 KEB014 KEB006 KEB010 KEB012 KEB018 Description Single Channel, Dual Supply, SOT23-5 for buffer-style pinout Single Channel, Dual Supply, SC70-5 for buffer-style pinout Dual Channel, Dual Supply, 8 lead SOIC Dual Channel, Dual Supply, 8 lead MSOP Quad Channel, Dual Supply, 14 lead TSSOP Quad Channel, Dual Supply, 14 lead SOIC Products LMV321AS5X LMV321AP5X LMV358AM8X LMV358AMU8X LMV324AMTC14X LMV324AM14X
Evaluation board schematics and layouts are shown in Figures 4 and 5.
Evaluation Board Schematic Diagrams
Figure 4a: LMV321 KEB013 schematic
Figure 4b: LMV321 KEB014 schematic
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LMV321/LMV358/LMV324
DATA SHEET
Evaluation Board Schematic Diagrams (Continued)
Figure 4c: LMV358 KEB006/KEB010 schematic
Figure 4d: LMV324 KEB012/KEB018 schematic
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DATA SHEET
LMV321/LMV358/LMV324
LMV321 Evaluation Board Layout
Figure 5a: KEB013 (top side)
Figure 5b: KEB013 (bottom side)
Figure 5c: KEB014 (top side)
Figure 5d: KEB014 (bottom side)
10
REV. 1A April 2004
LMV321/LMV358/LMV324
DATA SHEET
LMV358 Evaluation Board Layout
Figure 5e: KEB006 (top side)
Figure 5f: KEB006 (bottom side)
Figure 5g: KEB010 (top side)
Figure 5h: KEB010 (bottom side)
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11
DATA SHEET
LMV321/LMV358/LMV324
LMV324 Evaluation Board Layout
Figure 5i: KEB012 (top side)
Figure 5j: KEB012 (bottom side)
Figure 5k: KEB018 (top side)
Figure 5l: KEB018 (bottom side)
12
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LMV321/LMV358/LMV324
DATA SHEET
LMV321 Package Dimensions
SOT23-5
b C L e
DATUM 'A'
2
C L
E
C L
E1
e1 D C L
C
SYMBOL A A1 A2 b C D E E1 L e e1
MIN 0.90 0.00 0.90 0.25 0.09 2.80 2.60 1.50 0.35
MAX 1.45 0.15 1.30 0.50 0.20 3.10 3.00 1.75 0.55 0.95 ref 1.90 ref 0 10
NOTE:
1. All dimensions are in millimeters. 2 Foot length measured reference to flat foot surface parallel to DATUM 'A' and lead surface. 3. Package outline exclusive of mold flash & metal burr. 4. Package outline inclusive of solder plating. 5. Comply to EIAJ SC74A. 6. Package ST 0003 REV A supercedes SOT-D-2005 REV C.
A
A2
A1
SC70
b
C L
e
L
C L
HE
C L
E
Q1
SYMBOL e D b E HE Q1 A2 A1 A c L
MIN MAX 0.65 BSC 1.80 2.20 0.15 0.30 1.15 1.35 1.80 2.40 0.10 0.40 0.80 1.00 0.00 0.10 0.80 1.10 0.10 0.18 1.10 0.30
D C L
C
NOTE:
1. 2. 3. 4. All dimensions are in millimeters. Dimensions are inclusive of plating. Dimensions are exclusive of mold flashing and metal burr. All speccifications comply to EIAJ SC70.
A
A2
A1
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13
DATA SHEET
LMV321/LMV358/LMV324
LMV358 Package Dimensions
SOIC
D e ZD C L 7 SYMBOL A1 B C D E e H h L A ZD A2 L
SOIC-8
MIN MAX 0.10 0.25 0.36 0.46 0.19 0.25 4.80 4.98 3.81 3.99 1.27 BSC 5.80 6.20 0.25 0.50 0.41 1.27 1.52 1.72 8 0 0.53 ref 1.37 1.57
C L
E
H
Pin No. 1
B
DETAIL-A
h x 45
NOTE:
DETAIL-A 1. All dimensions are in millimeters. 2. Lead coplanarity should be 0 to 0.10mm (.004") max. 3. Package surface finishing: (2.1) Top: matte (charmilles #18~30). (2.2) All sides: matte (charmilles #18~30). (2.3) Bottom: smooth or matte (charmilles #18~30). 4. All dimensions excluding mold flashes and end flash from the package body shall not exceed o.152mm (.006) per side(d).
A
A1
A2
C
MSOP
e
S
02
MSOP-8
t1 R1 SYMBOL MIN A 1.10 A1 0.10 A2 0.86 D 3.00 D2 2.95 E 4.90 E1 3.00 E2 2.95 E3 0.51 E4 0.51 R 0.15 R1 0.15 t1 0.31 t2 0.41 b 0.33 b1 0.30 c 0.18 c1 0.15 01 3.0 02 12.0 03 12.0 L 0.55 L1 0.95 BSC aaa 0.10 bbb 0.08 ccc 0.25 e 0.65 BSC S 0.525 BSC MAX - 0.05 0.08 0.10 0.10 0.15 0.10 0.10 0.13 0.13 +0.15/-0.06 +0.15/-0.06 0.08 0.08 +0.07/-0.08 0.05 0.05 +0.03/-0.02 3.0 3.0 3.0 0.15 - - - - - -
E/2 2X
-H-
t2 R Gauge Plane
E1 3 7
0.25mm
-B-
2
03 b L1 c1 b1 Section A - A
5
L
01
E3 E4 1 2
2 4 6
ccc A B C c D2 A2
-C-
Detail A Scale 40:1 Detail A
E2
A b
aaa A bbb M A B C
-A-
A A E1 E
A1
D
3 4
NOTE:
1 All dimensions are in millimeters (angle in degrees), unless otherwise specified.
2 3 4 5 6 7
Datums - B - and - C - to be determined at datum plane - H - . Dimensions "D" and "E1" are to be determined at datum - H - . Dimensions "D2" and "E2" are for top package and dimensions "D" and "E1" are for bottom package. Cross sections A - A to be determined at 0.13 to 0.25mm from the leadtip. Dimension "D" and "D2" does not include mold flash, protrusion or gate burrs. Dimension "E1" and "E2" does not include interlead flash or protrusion.
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REV. 1A April 2004
LMV321/LMV358/LMV324
DATA SHEET
LMV324 Package Dimensions
TSSOP
2X E/2 1.0 DIA 1.0 b1 ddd C B A
2X N/2 TIPS 123 6 6 N 5
e
-B-
7
(b)
8
TSSOP-14
c1 SYMBOL A A1 A2 L R R1 b b1 c c1 01 L1 aaa bbb ccc ddd e 02 03 D E1 E e N MIN - 0.05 0.85 0.50 0.09 0.09 0.19 0.19 0.09 0.09 0 NOM - - 0.90 0.60 - - - 0.22 - - - 1.0 REF 0.10 0.10 0.05 0.20 0.65 BSC 12 REF 12 REF 5.00 4.40 6.4 BSC 0.65 BSC 14 MAX 1.10 0.15 0.95 0.75 - - 0.30 0.25 0.20 0.16 8
E1 E
c
1.0
e /2 9
SECTION AA
ccc
7 -A-
D8 3
A2 A
aaa C
-C-
b NX bbb M C B A
A1
(02) (0.20) R1
-H-
R
GAGE PLANE 10
4.90 4.30
5.10 4.50
A A
0.25
(03)
L (L1)
01
NOTES:
1 All dimensions are in millimeters (angle in degrees).
2 3 4 5
Dimensioning and tolerancing per ASME Y14.5-1994. Dimensions "D" does not include mold flash, protusions or gate burrs. Mold flash protusions or gate burrs shall not exceed 0.15 per side . Dimension "E1" does not include interlead flash or protusion. Interlead flash or protusion shall not exceed 0.25 per side. Dimension "b" does not include dambar protusion. Allowable dambar protusion shall be 0.08mm total in excess of the "b" dimension at maximum material condition. Dambar connot be located on the lower radius of the foot. Minimum space between protusion and adjacent lead is 0.07mm for 0.5mm pitch packages. Terminal numbers are shown for reference only. Datums - A - and - B - to be determined at datum plane - H - . Dimensions "D" and "E1" to be determined at datum plane - H - . This dimensions applies only to variations with an even number of leads per side. For variation with an odd number of leads per side, the "center" lead must be coincident with the package centerline, Datum A. Cross sections A - A to be determined at 0.10 to 0.25mm from the leadtip.
6 7 8 9 10
8 Lead
14 Lead
MAX 3.10 4.50 SYMBOL D E1 E e N MIN 4.90 4.30 NOM 5.00 4.40 6.4 BSC 0.65 BSC 14 MAX 5.10 4.50
7
16 Lead
SYMBOL D E1 E e N MIN NOM MAX SOIC-14 5.10 4.90 5.00 SYMBOL 4.40 MIN MAX 4.30 4.50 A1 .0098 6.4 .0040 BSC B .018 0.65 .014 BSC C .0075 .0098 16 D .337 .344 E .150 .157 e 28 Lead .050 BSC H .2284 .2440 MIN NOM MAX h .0099 .0196 9.50 9.70 9.80 L .016 .050 4.30 4.40 4.50 A .060 .068 6.4 BSC 8 0 0.65 BSC ZD 0.20 ref 28 A2 .054 .062
SOIC
SYMBOL D E1 E e N
MIN 2.90 4.30
e
NOM 3.0 4.40 D 6.4 BSC 0.65 BSC 8 C L
ZD
20 Lead
SYMBOL D E1 E e N Pin No. 1 MIN 6.50 4.30 NOM 6.50 4.40 6.4 BSC 0.65 BSC 20 B MAX C 6.60E H L 4.50 SYMBOL D E1 E e N
24 Lead
MIN 7.70 4.30 NOM 7.80 4.40 6.4 BSC 0.65 BSC 24 DETAIL-A MAX 7.90 4.50 SYMBOL D E1 E e N
L
h x 45
NOTE:
DETAIL-A 1. All dimensions are in inches. 2. Lead coplanarity should be 0 to 0.10mm (.004") max. 3. Package surface finishing: (2.1) Top: matte (charmilles #18~30). (2.2) All sides: matte (charmilles #18~30). (2.3) Bottom: smooth or matte (charmilles #18~30). 4. All dimensions excluding mold flashes and end flash from the package body shall not exceed o.152mm (.006) per side (d).
A
A1
A2
C
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15
DATA SHEET
LMV321/LMV358/LMV324
Ordering Information
Model LMV321 LMV321 LMV321 LMV358 LMV358 LMV324 LMV324 Part Number LMV321AP5X LMV321AP5X_NL LMV321AS5X LMV358AM8X LMV358AMU8X LMV324AMTC14X LMV324AM14X Lead Free Package SC70-5 SC70-5 SOT23-5 SOIC-8 MSOP-8 TSSOP-14 SOIC-14 Container Reel Reel Reel Reel Reel Reel Reel Pack Qty 3000 3000 3000 3000 3000 2500 2500
Temperature range for all parts: -40C to +125C.
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICES TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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(c) 2004 Fairchild Semiconductor Corporation

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